Title: Research in Radiation Harden by Design in nano-scale CMOS

Time: 04/18, Monday 14:30-15:30

Place: Room 401

Speaker: Herming Chiueh, Associate Professor

Department of Electrical and Computer Engineering, 

National Chiao Tung University, Hsinchu, Taiwan

 

Abstract of Talk:

Radiation harden by design is the preferred methodology in modern CMOS circuits for satellite and aviation applications. The phenomena caused by radiation particles on chips can be divided into two major categories. 1) A long-time exposure to radiation will induce cumulative effects. 2) Interaction with a single particle will induce single-event upsets (SEUs). The cumulative effects will lead to leakage currents, and the layout style of enclosed layout transistors (ELTs) is a solution to avoid it. In addition, there are many methods to mitigate the effect of SEUs in the previous work, including dual interlocked storage cell (DICE), triple-mode redundancy (TMR), built-in soft error resilience (BISER) [4], and error-correcting code (ECC). ECC is usually used in SRAM protection, and the others are used in sequential or combinational components. These techniques separately focus on architecture, circuit, or layout level to improve their radiation-hardened capability, but they incur delay, area, and power overheads at the same time. In this research, we combine the above techniques and integrated these circuit techniques into modern CMOS digital design flow. A Rad-Hard OpenRISC processor was implemented in 0.18um and 90nm CMOS processor, the experimental result applying heavy-ions has validated the effeteness of design methodology. In this talk, we will discuss the designed methodology and experimental results conducted in Berkeley Lawrence Lab as well as KU Leuven in 2014 and 2015.

 

 

Biography

Herming Chiueh received his B.S. degree in Electrophysics from National Chiao Tung University, Hsinchu, Taiwan, and the M.S. and Ph.D. degrees in Electrical Engineering from University of Southern California, Los Angeles, CA, USA. From 1996 to 2002, he was with Information Sciences Institute, University of Southern California, Marina del Rey, CA, USA. He has participated in the VLSI effort on several large projects in USC/ISI, which includes the development of a 55-million transistor processing-in-memory (PIM) chip. From 2009 to 2015, he has given more than 30 invited talks regarding his recent research in “closed-loop epileptic seizure detection” and “low-power sigma-delta data converters” in conferences and workshops as well as difference campuses and research institutes. He was the co-recipient of ISSCC 2013 Distinguished-Technical-Paper Award and ISSCC 2013 Demonstration Session Certificate of Recognition to recognize his research in “closed-loop neural-prosthetic SoC.” He currently serves as an Associate Professor in the Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan. His research interests include system-on-chip design methodology, low-power integrated circuits, neural interface circuits, and biomimetic systems.

Dr. Chiueh served as Demonstrations Chair on 2012 IEEE Biomedical Circuits and Systems Conferences (BIOCAS 2012,) Conference Secretariat on 2007 IEEE SOC Conference, and Finance Chair on 2007 IEEE International Workshop on Memory Technology, Design and Testing. He is member of Technical Committee on “Biomedical and Life Science Circuits and Systems” and “Nanoelectronics and Gigascale” in IEEE Circuits and Systems Society. He also served as Education Affairs Officer in IEEE Circuits and Systems Society, Taipei Chapter in 2011. He was member of technical program committee and session chair in several conferences, such as ISCAS, MWSCAS, THERMINIC, APSCAS, THETA, and ICECS.

 

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